The data processing apparatus maps the input symbols to be communicated onto a predetermined number of carrier signals of an orthogonal frequency division multiplexing (OFDM) symbol. The data processing apparatus includes an interleaver memory that reads in a predetermined number of data symbols for mapping onto OFDM carrier signals. The interleaver memory reads out data symbols on OFDM carriers for mapping, the read-out being done in a different order than the read-in, the order being determined from the address set, the data symbols Are interleaved on the carrier signals. The set of addresses is generated from an address generator that includes a linear feedback shift register and a permutation circuit. To provide 4k mode for OFDM modulation systems such as digital video broadcasting (DVB) standards, such as DVB-ground (DVB-T) standards or DVB-handheld (DVB-H) standards, The generator polynomials for linear feedback shift registers are provided with the permutation order established by simulation analysis to optimize communication performance over typical wireless channels.



Orthogonal Frequency Division Multiplexing, Interleaver Memory, Lead-Out, Lead-in, Linear Feedback Shift Register, Permutation Circuit, DVB-Ground Standard, DVB-Handheld Standard