ES2304757T3

Title

Not Available

Application Number:

ES20060075518T

Publication Date:

16-10-2008

Current Assignee:

Family ID:

Application Date:

23-03-2004

Declaring Company:

Publication Country:

US

Priority Date:

25-03-2003

Title

Not Available

Application Number:

ES20060075518T

Family ID:

Publication Country:

US

Publication Date:

16-10-2008

Application Date:

23-03-2004

Priority Date:

25-03-2003

Current Assignee:

Declaring Company:

Abstract  Abstract

A data processing apparatus that functions to correlate input symbols, to be communicated in a predetermined number of carrier signals of an orthogonal frequency division multiplexed (Orthogonal Frequency Division Multiplexed) symbol, comprising the data processing apparatus : an interleaving memory that functions to enter in it the predetermined number of data symbols to be correlated in the OFDM carrier signals, and read the data symbols for the OFDM carriers in order to perform the correlation, the reading being carried out in an order different from that of the introduction, the order being determined by a set of addresses, with the effect that the data symbols are interleaved in the carrier signals; an address generator that functions to generate the set of addresses, an address being generated for each of the input symbols, in order to indicate one of the carrier signals in which the data symbol has to be correlated, comprising the address generator: a linear displacement register with feedback that includes a predetermined number of registration stages, and which functions to generate a pseudo-random sequence of bits according to a generator polynomial; a permutation circuit that functions to receive the contents of the shift register stages, and permute the bits present in the registration stages according to a permutation order, in order to form an address of one of the OFDM carriers; and a control unit that operates in combination with an address checking circuit, to regenerate an address when a generated address exceeds a predetermined maximum valid address characterized in that the predetermined maximum valid address is three thousand twenty four; the linear displacement register with feedback has eleven registration stages with a generator polynomial for the linear displacement register with feedback, of Ri (10) = Ri - 1 (0) oplus Ri - 1 (2), and the permutation order forms an eleven bit Ri (n) address for the order data symbol i of the bit present in the nth registration stage, Ri (n), according to the table : (See table)

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Explicitly disclosed patent:openly and comprehensibly describes all details of the invention in the patent document.

Implicitly disclosed patent:does not explicitly state certain aspects of the invention, but still allows for these to be inferred from the information provided.

Basis patent:The core patent in a family, outlining the fundamental invention from which related patents or applications originate.

Family member:related patents or applications that share a common priority or original filing.