A transmitter for transmitting data using orthogonal frequency division multiplexing, OFDM, including the transmitter a data processing apparatus that functions to correlate input symbols, to be communicated in a predetermined number of carrier signals of a division multiplexed symbol Orthogonal Frequency Division Multiplexed orthogonal frequency according to a plurality of different operating modes, each of which provides a different number of OFDM carriers, the data processing apparatus comprising: an interleaving memory that functions to insert into it the predetermined number of data symbols to be correlated in the OFDM carrier signals, and read the data symbols for the OFDM carriers in order to perform the correlation, the reading being performed in a different order from the introduction, being determined the order through a set of addresses, with the effect that the data symbols are interleaved in the carrier signals; an address generator that functions to generate the set of addresses, an address being generated for each of the input symbols, in order to indicate one of the carrier signals in which the data symbol has to be correlated, comprising the address generator: a linear displacement register with feedback that includes a predetermined number of registration stages, and which functions to generate a pseudo-random sequence of bits according to a generator polynomial; a permutation circuit that functions to receive the contents of the shift register stages, and permute the bits present in the registration stages according to a permutation order, in order to form an address of one of the OFDM carriers; and a control unit that works in combination with an address checking circuit, to regenerate an address when a generated address exceeds the predetermined number of carriers; characterized in that the transmitter can be switched between operating modes 2k, 4k and 8k, and because for 4k mode the default number of OFDM carrier signals is three thousand and twenty four; the linear displacement register with feedback has eleven registration stages with a generator polynomial for the linear displacement register with feedback, of Ri (10) = Ri-1 (0) Phi Ri-1 (2), and the permutation order forms an eleven bit R i (n) address for the order data symbol i of the bit present at the nth registration stage, Ri (n), in accordance with the table: (See table)