Data processing apparatus that can be operated to establish correspondences of input symbols, which are to be communicated, on a predetermined number of carrier signals of a symbol Multiplexed by Orthogonal Frequency Division, OFDM, comprising the data processing apparatus an interleaving memory that can be operated to enter therein the predetermined number of data symbols for mapping on OFDM carrier signals, and read the data symbols for OFDM carriers for the purpose of mapping , the reading being carried out in a different order from that of the introduction, the order being determined from a set of addresses, with the result that the data symbols are interleaved in the carrier signals, an address generator that can be operated to generate the set of addresses, being generated an address ion for each of the input symbols in order to indicate one of the carrier signals on which the correspondence of the data symbol is to be established, the address generator comprising a shift register with linear feedback that includes a predetermined number of recording stages, and that can be operated to generate a pseudo-random sequence of bits according to a generator polynomial, a permutation circuit that can be operated to receive the content of the stages of the shift register, and to permute the bits present in the registration stages in a permutation order in order to form an address of one of the OFDM carriers, and a control unit that can be operated in combination with an address checking circuit to regenerate a address when a generated address exceeds a maximum valid address determined by the default number Carrier termination, characterized in that the predetermined number of OFDM carrier signals is a maximum of four thousand and ninety-six, the displacement register with linear feedback has eleven registration stages with a generator polynomial for the displacement register with linear feedback of R i (10) = Ri-1 (0) ⊕ Ri-1 (2), and the permutation order forms an eleven bit address Ri (n) for the ith data symbol from the bit present in the nth registration stage Ri (n) according to the table: ** (See formula) **