A data processing apparatus that functions to correlate input symbols to be communicated in a predetermined number of carrier signals of a symbol multiplexed by orthogonal frequency division OFDM (Orthogonal Frequency Division Multiplexed), the data processing apparatus comprising: an interleaving memory that functions to enter in it the predetermined number of data symbols to be correlated in the OFDM carrier signals, and read the data symbols for the OFDM carriers in order to perform the correlation, the reading being carried out in a order different from that of the introduction, the order being determined by a set of addresses, with the effect that the data symbols are interleaved in the carrier signals; an address generator that functions to generate the set of addresses, an address being generated for each of the input symbols, in order to indicate one of the carrier signals in which the data symbol has to be correlated, the address generator: a linear displacement register with feedback that includes a predetermined number of registration stages, and that functions to generate a pseudo-random sequence of bits according to a generator polynomial; a permutation circuit that functions to receive the contents of the shift register stages, and permute the bits present in the registration stages according to a permutation order, in order to form an address of one of the OFDM carriers; and a control unit that works in combination with an address checking circuit, to regenerate an address when a generated address exceeds a maximum valid address determined by the predetermined number of carriers; characterized in that the predetermined number of OFDM carrier signals is a maximum of four thousand ninety-six, the linear displacement register with feedback has eleven registration stages with a generating polynomial for the linear displacement register with feedback, of Ri ( 10) = Ri-1 (0) zeta Ri-1 (2), and the permutation order forms, with an additional bit, a twelve-bit address, which includes an address Ri (n) of eleven bits for the order data symbol i of the bit present in the nth registration stage, Ri (n), according to the table: and the additional bit is the most significant bit of the address, being switched or alternating the value of the additional bit between 0 and 1 between the consecutively generated addresses.